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Grid side wall imaging method

A gate sidewall and patterning technology, applied in electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of increased production cost and complex process flow, and achieve the effect of reducing production cost and simplifying process flow

Active Publication Date: 2014-05-28
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Aiming at the above existing problems, the present invention discloses a gate spacer patterning method to overcome the problem of excessive thickness of the silicon nitride film in the prior art to solve the high stress via etch stop layer process. Voids that may cause serious problems in the subsequent process, using the SPT process to remove the main sidewall made of silicon dioxide or silicon oxide can expand the filling space of silicon nitride and solve the problem of voids, but because the current SPT process requires a specific etching chamber It can only be carried out, which leads to the problem of complicated process and increased production cost

Method used

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Embodiment 1

[0035] Such as Figure 1-5 As shown, this implementation involves a method for patterning gate sidewalls, including the following steps:

[0036] S1, providing a semiconductor structure 1 having a gate 2 and a first spacer 4 covering the sidewall of the gate 2, the semiconductor structure 1 also has a shallow trench isolation 3 (STI, shallow trench isolation), and the gate 2 includes a polysilicon gate 21 and gate oxide layer 22.

[0037] S2, prepare a polycrystalline carbon layer 5 to cover the surface of the semiconductor structure 1, the polycrystalline carbon layer 5 covers the top wall of the gate 2, the surface of the first spacer 4, the surface of the shallow trench isolation 3 and the exposed surface of the semiconductor structure 1 .

[0038] S3, partially remove the polycrystalline carbon layer 5 to form the second sidewall 51 of the gate 2 on the surface of the first sidewall 4, that is, etch the polycrystalline carbon layer 5 to form the first sidewall 51 forming...

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Abstract

The invention discloses a grid side wall imaging method. The method comprises the steps that a semiconductor structure which has a grid and a first side wall which covers the side wall of the grid is provided; a polycrystalline carbon layer is prepared to cover the surface of the semiconductor structure; the polycrystalline carbon layer is partially removed, so that a second side wall of the grid is formed on the surface of the first side wall; after a source drain implantation process is carried out on the semiconductor structure, the second side wall is removed; and a source drain annealing technology is continued. According to the grid side wall imaging method provided by the invention, through oxygenated plasma treatment, a polycrystalline carbon side wall which is used as a main side wall can be neatly removed; without using an SPT process which needs to be carried out in a specific etching cavity, the problem of void in a high stress through hole etching stop layer process can be solved; a process flow is simplified; and the production cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for patterning gate sidewalls. Background technique [0002] In the semiconductor development process, an integrated circuit (IC for short) often includes millions of electronic devices. In ultra-large-scale integrated circuits, tens of thousands to millions of transistors are integrated on a silicon wafer of only a few millimeters square. [0003] With the further shrinking of the device size, its manufacturing process requirements are also undergoing major challenges. Therefore, new processes including high-stress via etch stop layer (CESL), high k / metal gate and ultra low k have been introduced in the semiconductor manufacturing process to improve device performance and meet the development of semiconductor technology. [0004] Among them, the filling of silicon nitride in the CESL process is an important challenge in semiconductor technology. B...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336
CPCH01L21/28008H01L29/401H01L29/6656
Inventor 周军
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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