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Methods for delta-QP signaling for decoder parallelization in hevc

a decoder and parallelization technology, applied in signal generators with optical-mechanical scanning, color televisions with bandwidth reduction, etc., can solve the problems of significant increase in the length of the decoding pipeline, inability to reconstruct cub>0/b>, and difficulty in hardware decoding standard dqp syntax

Active Publication Date: 2012-07-19
SONY GRP CORP
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  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method and apparatus for integrating a delta quantization parameter (DQP) into a bitstream of a video coding unit. By placing the DQP after mode information or coded block flags, the method and apparatus allow for parallel processing of multiple coding units within a larger coding unit, leading to improved performance and efficiency. The technical effects of the patent include improved video coding quality and faster processing times. The method and apparatus can be used in various devices such as personal computers, laptops, servers, and smart appliances.

Problems solved by technology

The standard DQP syntax introduces difficulty in hardware decoding.
On one hand placing DQP at the end of an LCU could introduce delay in decoding, which means, when C0 is entropy-decoded, reconstruction of CU0 is not possible until the DQP value is read.
This will significantly increase the length of a decoding pipeline.
On the other hand, the DQP is unnecessarily sent with the standard syntax.
But the standard syntax still signals DQP, which is a waste of bits.

Method used

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Embodiment Construction

[0024]To improve the Delta Quantization Parameter (DQP) syntax, several possibilities exist. Specifically, the location of the DQP signaling is placed in different locations in the Largest Coding Unit (LCU) bitstream. By moving the DQP signaling, the decoder pipelining issue is resolved.

[0025]FIG. 2 illustrates a diagram of a modified LCU syntax according to some embodiments. When the LCU is coded in the SKIP mode, then no DQP is sent. However, in the modified LCU syntax 200, the DQP 202 is positioned immediately after the mode information (M0) of the first CU if the LCU is not coded in the SKIP mode. With this change, decoder pipelining is enabled (e.g. after entropy decoding of CU0, CU0 is able to be reconstructed immediately, while the entropy decoder is able to simultaneously proceed to decode CU1).

[0026]FIG. 3 illustrates a diagram of a modified LCU syntax according to some embodiments. When all of the Coding Units (CUs) within the LCU are coded in the SKIP mode, there is no DQ...

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Abstract

By implementing a new bitstream for a Delta-Quantization Parameter (DQP), a decoder is able to implement parallel decoding of multiple coding units within a largest coding unit. In some embodiments, the DQP is placed immediately after the mode information of the first coding unit. In some embodiments, the DQP is placed after the mode information of the first non-skipped coding unit. In some embodiments, the DQP is placed after the first non-zero coded block flag.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)[0001]This application claims priority under 35 U.S.C. §119(e) of the U.S. Provisional Patent Application Ser. No. 61 / 433,039, filed Jan. 14, 2011 and titled, “CHANGING BITSTREAM SYNTAX FOR DELTA-QP SIGNALING FOR DECODER PARALLELIZATION IN HEVC.” The Provisional Patent Application, Ser. No. 61 / 433,039, filed Jan. 14, 2011 and titled, “CHANGING BITSTREAM SYNTAX FOR DELTA-QP SIGNALING FOR DECODER PARALLELIZATION IN HEVC” is also hereby incorporated by reference in its entirety for all purposes.FIELD OF THE INVENTION[0002]The present invention relates to the field of image processing. More specifically, the present invention relates to methods for delta-qp signaling for decoder parallelization in High Efficiency Video Coding (HEVC).BACKGROUND OF THE INVENTION[0003]In Advanced Video Coding (AVC), changing a quantization parameter (referred to as Delta Quantization Parameter (DQP)) is allowed at the macroblock level for better rate control and reg...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04N7/12
CPCH04N19/159H04N19/70H04N19/436H04N19/44H04N19/46
Inventor LIU, WEIDONG, LINA
Owner SONY GRP CORP
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